1. Field of the Invention
The present invention relates to a memory array and addressing circuitry for use therewith. More particularly, the invention relates to improved bit decoding, restoring and word decoding circuitry for a static random access memory (RAM) array. The invention may be implemented in BICMOS technology.
2. Description of the Related Art
Various bit decoding (also known as column decoding or selection) and word decoding (also known as row decoding or selection) schemes for memory arrays are known in the art. See, for example: Aoyama et al. U.S. Pat. No. 4,198,700; White U.S. Pat. No. 4,330,851; Tanimura U.S. Pat. No. 4,429,374; Chan et al. U.S. Pat. No. 4,578,779; Chan et al. U.S. Pat. No. 4,596,002; Chan U.S. Pat. No. 4,598,390; Ochii U.S Pat. No. 4,612,631; Sauer U.S. Pat. No. 4,639,898; and Chan et al. U.S. Pat. No. 4,752,913.
Chan et al. U.S. Pat. No. 4,752,913 (particularly FIGS. 5, 6, and 9) discloses improved bit decoder, bit select, word decoder and other circuits for use in an all-bipolar RAM employing CTS (complementary transistor switch) cells. Decoder circuitry for an all-CMOS static RAM is disclosed in Aoyama et al. U.S. Pat. No. 4,198,700 (particularly FIG. 6).
These and other prior art decoding schemes have, however, served specialized needs not applicable to CMOS or BICMOS static RAMs, or have suffered from several disadvantages. For example, a decode scheme for an all-bipolar array normally will not be able (and does not need) to provide a restore or precharge signal to the bit lines after a read or write operation. A restore signal is, however, needed for high-speed operation of a CMOS or BICMOS array. This restore signal also must be timed properly with the bit decode signal, and the restore timing circuitry (clock drivers, etc.) normally consists of separate circuitry in the prior art, which has increased cost and complexity.
All-bipolar decoders also draw large amounts of power and occupy considerable chip area. On the other hand, although all-CMOS decoders draw less power and are smaller, they are usually slower.
With the increasing size and complexity of memories, the associated addressing circuitry has likewise become increasingly complex. Thus, there is an increasing need to simplify functions and reduce circuitry wherever possible, as well as a need to reduce power, increase speed and increase circuit density.